1. Field of the Invention
This invention relates to computer systems and, more particularly, to asynchronous data transfers between computer subsystems clocked at dissimilar clock rates by using a first-in-first-out (FIFO) buffer having a read interface, a write interface, and one or more data slots.
2. Description of Related Art
Some types of electrical systems operate in multiple “clock domains.” Each clock domain is associated with a clock signal that operates at a distinct frequency. For example, a microprocessor may possess a core clock domain and a secondary clock domain. The core clock domain may be associated with a core clock signal that operates at a higher frequency than a secondary clock signal associated with the secondary clock domain. Within the core clock domain, hardware components, such as memory controllers and serializers, may operate at the frequency associated with the core clock. Within the secondary clock domain, other hardware components, such as external memory units and controllers, may operate at the frequency associated with the secondary clock.
To facilitate communication between hardware components operating in different clock domains, data may be transferred from a first clock domain to a second clock domain using the higher frequency clock signal to synchronize the transfer. For example, a first clock domain may operate at 200 megahertz (MHz) and a second clock domain may operate at 100 MHz. Data may be transferred between the first and second clock domains by generating a clock enable signal based on the clock signal associated with the higher frequency, first clock domain. The clock enable signal typically indicates when the rising edges of the first and second clocks are aligned. Thus, data transferred using the clock enable signal is said to be “synchronized” with both clock signals, thereby enabling proper transmission of data.
However, synchronizing data transfers in the preceding manner may not permit the hardware components to send and receive data at a desired rate. In addition, various meta-stability issues may arise when transferring data in the described manner. For example, setup and hold times associated with various logic components, such as flip-flops and registers, may be violated while synchronizing a transfer, thereby causing unreliable results. Overcoming the meta-stabililty issues and the undesirable transfers rates associated with data transfers between multiple clock domains has yet to be resolved.